Reliability-Aware Design for Nanometer-Scale Devices, January 2008Report as inadecuate

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Presented at: Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, January 21-24, 2008 Published in: Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC) Publication date: 2008

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges to maintain manufacturing yield rates and reliable devices in their expected lifetimes for latest nanometer-scale dimensions. In fact, new system and processor microarchitectures require new reliability-aware design methods and exploration tools that can face these challenges without significantly increasing manufacturing cost, reducing system performance or imposing large area overheads due to redundancy. In this paper we overview the latest approaches in reliability modeling and variability-tolerant design for latest technology nodes, and advocate the need of reliability-aware design for forthcoming consumer electronics. Moreover, we illustrate with a case study of an embedded processor that effec- tive reliability-aware design can be achieved in nanometer-scale devices through integral design approaches that covers modeling and exploration of reliability effects, and hardware-software architectural techniques to provide reliability-enhanced solutions at both microarchitectural- and system-level.

Reference EPFL-CONF-117034View record in Web of Science

Author: Atienza, David; De Micheli, Giovanni; Benini, Luca; Ayala, José L.; Valle, Del; Pablo, G.; DeBole, Michael; Narayanan, Vijay


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