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Presented at: International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS), Tampere, Finland, October 7-12, 2012 Published in: Proceedingd of the International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS) Publication date: 2012

Achieving the main memory (DRAM) required bandwidth at ac- ceptable power levels for current and future applications is a ma- jor challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM mem- ories promise to provide a significant boost in bandwidth at low power levels by exploiting multiple channels and wide data inter- faces. In this paper, we address the problem of efficiently exploit- ing the multiple channels provided by standard (JEDEC’s WIDE- IO) 3D-stacked memories, to extract maximal effective bandwidth and minimize latency for main memory access. We propose a new distributed interleaved access method that leverages the on-chip in- terconnect to simplify the design and implementation of the DRAM controller, without impacting performance compared to traditional centralized implementations. We perform experiments on realis- tic workload for a mobile communication and multimedia platform and show that our proposed distributed interleaving memory access method improves the overall throughput while minimally impact- ing the performance of latency sensitive communication flows.

Keywords: NoC ; WideIO ; DRAM controller ; interleaving Reference EPFL-CONF-180198





Autor: Seiculescu, Ciprian; Benini, Luca; De Micheli, Giovanni

Fuente: https://infoscience.epfl.ch/record/180198?ln=en



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