Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCLReportar como inadecuado

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Published in: IEEE Transactions on Circuits and Systems II, vol. 59, num. 12, p. 903-907 Piscataway: Ieee-Inst Electrical Electronics Engineers Inc, 2012

Power-frequency scaling in subthreshold source coupled logic (STSCL) systems has been studied and analyzed. It is shown that the operating frequency of such systems can be adjusted over about three decades with linearly proportional power dissipation. The heart of such a system is a phase-locked loop (PLL)-based clock generator (CG) with a very wide tuning range controlling the dynamics of the STSCL system. The design of a wide tuning range PLL utilizing a novel self-adjustable loop filter that generates the reference clock as well as the bias current for the STSCL system is described. The PLL-based CG exhibits linear power-frequency characteristics in order to minimize its power consumption overhead (7 pJ with 350 nA standby current). Implemented in 0.13 μm CMOS, the CG occupies 0.06 mm2 with a supply voltage that can be reduced down to VDD = 0.9 V.

Keywords: current-mode logic (CML) ; energy consumption ; phase-locked loop (PLL) ; power management ; source-coupled logic (SCL) ; subthreshold CMOS ; subthreshold SCL (STSCL) Reference EPFL-ARTICLE-184987doi:10.1109/Tcsii.2012.2231032View record in Web of Science

Autor: Tajalli, Seyed Armin; Leblebici, Yusuf

Fuente: https://infoscience.epfl.ch/record/184987?ln=en

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