Single-FPGA, Scalable, Low-Power, and High-Quality 3D Ultrasound BeamformerReportar como inadecuado




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Presented at: 26th International Conference on Field-Programmable Logic and Applications (FPL), Lausanne, Switzerland, August 29 - September 2, 2016 Published in: Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL) Series: International Conference on Field Programmable and Logic Applications New York: Ieee, 2016

We present an efficient FPGA architecture suitable for a medical 3D ultrasound beamformer. We tackle the delay calculation bottleneck, which is the heart and the most critical part of the beam-former, by proposing a computationally efficient design that is able to perform volumetric real-time beamforming on a single-chip FPGA. The design has been demonstrated for a 32×32-channel receive probe, and we extrapolated the requirements of the architecture for 80×80 channels.

Reference EPFL-CONF-224461View record in Web of Science





Autor: Simon, W.; Yüzügüler, Ahmet Caner; Ibrahim, Aya; Angiolini, Federico; Arditi, Marcel; Thiran, Jean-Philippe; De Micheli, Giovan

Fuente: https://infoscience.epfl.ch/record/224461?ln=en







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