Comparative Analysis of 6T, 7T, 8T, 9T, and 10T Realistic CNTFET Based SRAMReport as inadecuate

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Journal of Nanotechnology - Volume 2017 2017, Article ID 4575013, 9 pages -

Research Article

Department of Computer Science and Engineering, Oakland University, Rochester, MI, USA

Department of Computer Science, University of Tabuk, Tabuk, Saudi Arabia

Correspondence should be addressed to Shital Joshi

Received 4 January 2017; Accepted 16 February 2017; Published 15 March 2017

Academic Editor: Hongmei Luo

Copyright © 2017 Shital Joshi and Umar Alabawi. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


CMOS technology below 10 nm faces fundamental limits which restricts its applicability for future electronic application mainly in terms of size, power consumption, and speed. In digital electronics, memory components play a very significant role. SRAM, due to its unique ability to retain data, is one of the most popular memory elements used in most of the digital devices. With aggressive technology scaling, the design of SRAM is seriously challenged in terms of delay, noise margin, and stability. This paper compares the performance of various CNTFET based SRAM cell topologies like 6T, 7T, 8T, 9T, and 10T cell with respect to static noise margin SNM, write margin WM, read delay, and power consumption. To consider the nonidealities of CNTFET, variations in tube diameter and effect of metallic tubes are considered for various structures with respect to various performance metrics like SNM, WM, read delay, and power consumption.

Author: Shital Joshi and Umar Alabawi



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