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Journal of NanomaterialsVolume 2011 2011, Article ID 906237, 6 pages

Research Article

School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Engineering Campus, 11800 Penang, Malaysia

Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Malaysia

Department of Computer Engineering, Islamic Azad University, Ashtian Branch, 39618-13347 Ashtian, Iran

Received 10 January 2011; Accepted 27 February 2011

Academic Editor: Theodorian Borca-Tasciuc

Copyright © 2011 M. H. Ghadiry et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A novel full adder circuit is presented. The main aim is to reduce power delay product PDP in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.

Autor: M. H. Ghadiry, Asrulnizam Abd Manaf, M. T. Ahmadi, Hatef Sadeghi, and M. Nadi Senejani



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