Full Hardware Implementation of Short Addition Chains Recoding for ECC Scalar MultiplicationReportar como inadecuado

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1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE 2 IMATH - Institut de Mathématiques de Toulon - EA 2134

Abstract : Ensuring uniform computation profiles is an efficient protection against some side channel attacks SCA in embedded systems. Typical elliptic curve cryptography ECC scalar multiplication methods use two point operations addition and doubling scheduled according to secret scalar digits. Euclidean addition chains EAC offer a natural SCA protection since only one point operation is used. Computing short EACs is considered as a very costly operation and no hardware implementation has been reported yet. We designed an hardware recoding unit for short EACs which works concurrently to scalar multiplication. It has been integrated in an in-house ECC processor on various FPGAs. The implementation results show similar computation times compared to non-protected solutions, and faster ones compared to typical protected solutions e. g. 18 % speed-up over 192 b Montgomery ladder.

Keywords : addition chains counter-measure side channel attack scalar multiplication elliptic curve cryptography

Autor: Julien Proy - Nicolas Veyrat-Charvillon - Arnaud Tisserand - Nicolas Méloni -

Fuente: https://hal.archives-ouvertes.fr/


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