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Communication, FPGA, Preamble

Son, Eric Tien Tze

Supervisor and department: Gaudet, Vincent Electrical and Computer Engineering

Examining committee member and department: Schlegel, Christian Computing Science Cockburn, Bruce Electrical and Computer Engineering

Department: Electrical and Computer Engineering

Specialization:

Date accepted: 2009-10-02T15:26:52Z

Graduation date: 2009-11

Degree: Master of Science

Degree level: Master's

Abstract: This thesis describes the implementation of the physical layer for an experimental low-power wireless communication device. The system utilizes differential coherent correlation and threshold-based detection to produce a robust random-access packet-based communications protocol. Prior to implementing the system in hardware, the detection algorithm was rigorously simulated with a software model in C. The simulations revealed the tradeoffs between the packet miss performance and different system parameters such as input bit precision and threshold value. Having determined a suitable configuration, the detection algorithm was implemented on an FPGA platform. The focus of the FPGA design was on throughput and resource utilization. The final system utilizes approximately 6% of the slices available on a Xilinx Virtex II XC2V8000 FPGA and has a throughput of about 5 MChips-Second.

Language: English

DOI: doi:10.7939-R32Q60

Rights: License granted by Eric Son eson@ualberta.ca on 2009-09-30T17:43:01Z GMT: Permission is hereby granted to the University of Alberta Libraries to reproduce single copies of this thesis and to lend or sell such copies for private, scholarly or scientific research purposes only. Where the thesis is converted to, or otherwise made available in digital form, the University of Alberta will advise potential users of the thesis of the above terms. The author reserves all other publication and other rights in association with the copyright in the thesis, and except as herein provided, neither the thesis nor any substantial portion thereof may be printed or otherwise reproduced in any material form whatsoever without the author's prior written permission.





Autor: Son, Eric Tien Tze

Fuente: https://era.library.ualberta.ca/


Introducción



University of Alberta Simulation of Quantization Noise Effects on the Performance of a Wireless Preamble Detector and Demonstration of a Functional FPGA Prototype by Eric Tien Tze Son A thesis submitted to the Faculty of Graduate Studies and Research in partial fulfillment of the requirements for the degree of Master of Science Department of Electrical and Computer Engineering © Eric Tien Tze Son Fall 2009 Edmonton, Alberta Permission is hereby granted to the University of Alberta Libraries to reproduce single copies of this thesis and to lend or sell such copies for private, scholarly or scientific research purposes only.
Where the thesis is converted to, or otherwise made available in digital form, the University of Alberta will advise potential users of the thesis of these terms. The author reserves all other publication and other rights in association with the copyright in the thesis and, except as herein before provided, neither the thesis nor any substantial portion thereof may be printed or otherwise reproduced in any material form whatsoever without the authors prior written permission. Examining Committee Dr.
Vincent Gaudet, Electrical and Computer Engineering Dr.
Christian Schlegel, Computing Science Dr.
Bruce Cockburn, Electrical and Computer Engineering Abstract This thesis describes the implementation of the physical layer for an experimental low-power wireless communication device. The system utilizes differential coherent correlation and threshold-based detection to produce a robust random-access packet-based communications protocol. Prior to implementing the system in hardware, the detection algorithm was rigorously simulated with a software model in C. The simulations revealed the tradeoffs between the packet miss performance and different system parameters such as input bit precision and threshold value. Having determined a suitable configuration, the detection algorithm was implemented on an FPGA platform.
The focus of the...





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