Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits - Computer Science > Hardware ArchitectureReportar como inadecuado




Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits - Computer Science > Hardware Architecture - Descarga este documento en PDF. Documentación en PDF para descargar gratis. Disponible también para leer online.

Abstract: In nanometer scaled CMOS devices significant increase in the subthreshold,the gate and the reverse biased junction band-to-band-tunneling BTBT leakage,results in the large increase of total leakage power in a logic circuit.Leakage components interact with each other in device level through devicegeometry, doping profile and also in the circuit level through nodevoltages. Due to the circuit level interaction of the different leakagecomponents, the leakage of a logic gate strongly depends on the circuittopology i.e. number and nature of the other logic gates connected to its inputand output. In this paper, for the first time, we have analyzed loading effecton leakage and proposed a method to accurately estimate the total leakage in alogic circuit, from its logic level description considering the impact ofloading and transistor stacking.



Autor: Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy

Fuente: https://arxiv.org/







Documentos relacionados