A Design Approach for Networks of Self-Sampled All-Digital Phase-Locked LoopsReport as inadecuate

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1 E3S - Supélec Sciences des Systèmes Gif-sur-Yvette 2 CIAN - Circuits Intégrés Numériques et Analogiques LIP6 - Laboratoire d-Informatique de Paris 6 3 CEA-LETI - Laboratoire d-Electronique et des Technologies de l-Information

Abstract : This paper addresses the problem of the stability and the performance analysis of N-nodes Cartesian networks of self-sampled all digital phase-locked loops. It can be demonstrated that under certain conditions such as filter coefficients value a global and a local synchronization can be obtained. Our approach to find the optimal conditions consists in analyzing an corresponding linear average system of the Cartesian network rather than constructing a piecewise-linear system which is extremely difficult to analysis. The constructed corresponding system takes into account the non-linearity of the network and especially the self-sampling property. It is then analyzed by linear performance criteria such as modulus margin to guarantee a robust stability of the Cartesian network. The reliability of our approach is proved by transient simulations in networks of different sizes.

Author: Jean-Michel Akré - Jérôme Juillard - Mohammad Javidan - Eldar Zianbetov - Dimitri Galayko - Anton Korniienko - Eric Colinet -

Source: https://hal.archives-ouvertes.fr/


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