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VLSI Design - Volume 1 1994, Issue 2, Pages 127-154

Laboratory for Computer-Aided Design, Indian Institute of Science, Bangalore, India

University of Illinois at Urbana-Champaign, Urbana, Illinois, USA

Received 11 May 1989; Revised 25 February 1990

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

Autor: S. K. Nandy and R. B. Panwar



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