Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded SystemReport as inadecuate

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International Journal of Reconfigurable Computing - Volume 2014 2014, Article ID 806237, 8 pages -

Research ArticleDepartment of Electrical Engineering, COMSATS Institute of Information and Technology, Abbottabad, Pakistan

Received 28 July 2014; Revised 27 October 2014; Accepted 27 October 2014; Published 19 November 2014

Academic Editor: Nadia Nedjah

Copyright © 2014 Mohsin Amin et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We are proposing a design methodology for a fault tolerant homogeneous MPSoC having additional design objectives that include low hardware overhead and performance. We have implemented three different FT methodologies on MPSoCs and compared them against the defined constraints. The comparison of these FT methodologies is carried out by modelling their architectures in VHDL-RTL, on Spartan 3 FPGA. The results obtained through simulations helped us to identify the most relevant scheme in terms of the given design constraints.

Author: Mohsin Amin, Muhammad Shakir, Aqib Javed, Muhammad Hassan, and Syed Ali Raza

Source: https://www.hindawi.com/


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