Hardware-Efficient Design of Real-Time Profile Shape Matching Stereo Vision Algorithm on FPGAReportar como inadecuado

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International Journal of Reconfigurable Computing - Volume 2014 2014, Article ID 945926, 12 pages -

Research ArticleDepartment of Computer Engineering, Brigham Young University, Provo, UT 84602, USA

Received 7 October 2013; Revised 30 December 2013; Accepted 4 January 2014; Published 24 February 2014

Academic Editor: John Kalomiros

Copyright © 2014 Beau Tippetts et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A variety of platforms, such as micro-unmanned vehicles, are limited in the amount of computational hardware they can support due to weight and power constraints. An efficient stereo vision algorithm implemented on an FPGA would be able to minimize payload and power consumption in microunmanned vehicles, while providing 3D information and still leaving computational resources available for other processing tasks. This work presents a hardware design of the efficient profile shape matching stereo vision algorithm. Hardware resource usage is presented for the targeted micro-UV platform, Helio-copter, that uses the Xilinx Virtex 4 FX60 FPGA. Less than a fifth of the resources on this FGPA were used to produce dense disparity maps for image sizes up to 450 × 375, with the ability to scale up easily by increasing BRAM usage. A comparison is given of accuracy, speed performance, and resource usage of a census transform-based stereo vision FPGA implementation by Jin et al. Results show that the profile shape matching algorithm is an efficient real-time stereo vision algorithm for hardware implementation for resource limited systems such as microunmanned vehicles.

Autor: Beau Tippetts, Dah Jye Lee, Kirt Lillywhite, and James K. Archibald

Fuente: https://www.hindawi.com/


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