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International Journal of Reconfigurable Computing - Volume 2016 2016, Article ID 9128683, 8 pages -

Research Article

Department of EEE, BITS-Pilani, Pilani, Rajasthan 333031, India

Digital System Group, CEERI, Pilani, Rajasthan 333031, India

Received 30 September 2015; Accepted 11 January 2016

Academic Editor: Miriam Leeser

Copyright © 2016 Gaurav Purohit et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware HW implementation of new architecture uses Lookup Table LUT for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA.

Autor: Gaurav Purohit, Kota Solomon Raju, and Vinod Kumar Chaubey

Fuente: https://www.hindawi.com/


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