Series resistance effects in submicron MOS transistors operated from 300 K down to 4.2 KReport as inadecuate




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Abstract : In this paper low temperature electrical characterisation LTEC of submicron MOS transistors is proposed as an optional tool to investigate second-order effects. The LTEC allows to prove the link between the carrier multiplication at the source side and the series resistance effects. This link cannot be distinguished when the MOS transistor is operated at room temperature. This way one is able to do a further research on the series resistance effects and their impact on the extraction of the electrical parameters of submicron MOS transistors.





Author: E. Gutiérrez-D L. Deferm G. Declerck

Source: https://hal.archives-ouvertes.fr/



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