A 500-MS-s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain QuantizerReportar como inadecuado




A 500-MS-s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer - Descarga este documento en PDF. Documentación en PDF para descargar gratis. Disponible también para leer online.

This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ-conversion-step.

KEYWORDS

Time-Based ADC, Flash ADC, TDC, VTC, CMOS

Cite this paper

Ohhata, K. , Hotta, K. , Yamaguchi, N. , Hayakawa, D. , Sewaki, K. , Imayanagida, K. and Sonoda, Y. 2017 A 500-MS-s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer. Circuits and Systems, 8, 1-13. doi: 10.4236-cs.2017.81001.





Autor: Kenichi Ohhata, Kaihei Hotta, Naoto Yamaguchi, Daiki Hayakawa, Kenji Sewaki, Kento Imayanagida, Yuuki Sonoda

Fuente: http://www.scirp.org/



DESCARGAR PDF




Documentos relacionados