Multiscale EM and circuit simulation using the Laguerre-FDTD scheme for package-aware integrated-circuit designReportar como inadecuado


Multiscale EM and circuit simulation using the Laguerre-FDTD scheme for package-aware integrated-circuit design


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The objective of this research work is to develop an efficient methodology for chip-packagecosimulation. In the traditional design flow, the integrated circuit IC is first designedfollowed by the package design. The disadvantage of the conventional sequential designflow is that if there are problems with signal and power integrity after the integration ofthe IC and the package, it is expensive and time consuming to go back and change theIC layout for a different input-output IO pad assignment. To overcome this limitation,a concurrent design flow, where both the IC and the package are designed together, hasbeen recommended by researchers to obtain a fast design closure. The techniques from thisresearch work will enable multiscale cosimulation of the chip and the package making theconcurrent design flow paradigm possible.Traditional time-domain techniques, such as the finite-difference time-domain method,are limited by the Courant condition and are not suitable for chip-package cosimulation. TheCourant condition gives an upper bound on the time step that can be used to obtain stablesimulation results. The smaller the mesh dimension the smaller is the Courant time step. Inthe case of chip-package cosimulation the on-chip structures require a fine mesh, which canmake the time step prohibitively small. An unconditionally stable scheme using Laguerrepolynomials has been recommended for chip-package cosimulation. Prior limitations inthis method have been overcome in this research work. The enhanced transient simulationscheme using Laguerre polynomials has been named SLeEC, which stands for simulationusing Laguerre equivalent circuit. A full-wave EM simulator has been developed using theSLeEC methodology.A scheme for efficient use of full-wave solver for chip-package cosimulation has beenproposed. Simulation of the entire chip-package structure using a full-wave solver could bea memory and time-intensive operation. A more efficient way is to separate the chip-packagestructure into the chip, the package signal-delivery network, and the package power-deliverynetwork; use a full-wave solver to simulate each of these smaller subblocks and integratethem together in the following step, before a final simulation is done on the integratednetwork. Examples have been presented that illustrate the technique.



Georgia Tech Theses and Dissertations - School of Electrical and Computer Engineering Theses and Dissertations -



Autor: Srinivasan, Gopikrishna - -

Fuente: https://smartech.gatech.edu/







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