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This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functional elements can be dynamically allocated for application specific optimizations, enabling polymorphic computing. Using a modified network simulator, performance of several NoC topologies and parameters are investigated with standard benchmark programs, including fine grain and coarse grain computations. Simulation results highlight the flexibility and scalability of the proposed polymorphic NoC processor for a wide range of application domains.

KEYWORDS

Reconfigurable Computing; Network-on-Chip; Network Simulators; Polymorphic Computing

Cite this paper

J. Weber and E. Oruklu -A Reconfigurable Network-on-Chip Datapath for Application Specific Computing,- Circuits and Systems, Vol. 4 No. 2, 2013, pp. 181-192. doi: 10.4236-cs.2013.42025.





Autor: Joshua Weber, Erdal Oruklu

Fuente: http://www.scirp.org/



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