Pareto Points in SRAM Design Using the Sleepy Stack ApproachReportar como inadecuado


Pareto Points in SRAM Design Using the Sleepy Stack Approach


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Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for SRAM which occupies large transistor count in most state-of-the-art chip designs. We propose a novel ultra-low leakage SRAM design which we call -sleepy stack SRAM.- Unlike many other previous approaches, sleepy stack SRAM can retain logic state during sleep mode, which is crucial for a memory element. Compared to the best alternative we could find, a 6T SRAM cell with high-Vsubscript th transistors, the sleepy stack SRAM cell with 1.5xVsubscript th at 110-degree C achieves more than 5X leakage power reduction at a cost of 31% delay increase and 113% area increase. Alternatively, by widening wordline pass transistors, the sleepy stack SRAM cell can match the delay of the high-Vsubscript th 6T SRAM and still achieve 2.5X leakage power reduction at a cost of a 139% area penalty.



College of Computing Technical Reports -



Autor: Park, Jun Cheol - Mooney, Vincent John, III - -

Fuente: https://smartech.gatech.edu/







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