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The purpose of this dissertation is to design a 32 bits RISC microprocessor based on MIPS instructions and to do FPGA prototype verification. In this paper a 32-bit RISC Microprocessor of 34 MIPS instructions using VHDL is designed. Five stages viz. instruction fetch stage, instruction decode stage, execution stage, data memory stage and write back stage pipelining is used to improve the overall CPI Clock Cycles per Instruction. The data forwarding unit and hazard detection unit are adopted to solve data hazard. And to conquer the question of control hazard which is a result of the branch or jump instructions, comparer and forwarding unit are added in the instruction decode stage to reduce the delay of branches. The validity of this design is verified by soft simulations and FPGA prototype verification.

KEYWORDS

RISC microprocessor; pipeline; FPGA; control unit; simulator

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Autor: Zhibin Zou, Qinghai Zhang, Ming Ma

Fuente: http://www.scirp.org/



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