A 1,000 Frames-s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image ProcessorsReport as inadecuate




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State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China





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Abstract A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element PE array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames-s fps. A prototype chip with 64 × 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mm Standard CMOS process. The area size of chip is 1.5 mm × 3.5 mm. Each pixel size is 9.5 μm × 9.5 μm and each processing element size is 23 μm × 29 μm. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking. View Full-Text

Keywords: vision chip; image processing; machine vision; mathematical morphology vision chip; image processing; machine vision; mathematical morphology





Author: Qingyu Lin, Wei Miao, Wancheng Zhang, Qiuyu Fu and Nanjian Wu *

Source: http://mdpi.com/



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