A 12-Bit High-Speed Column-Parallel Two-Step Single-Slope Analog-to-Digital Converter ADC for CMOS Image SensorsReportar como inadecuado




A 12-Bit High-Speed Column-Parallel Two-Step Single-Slope Analog-to-Digital Converter ADC for CMOS Image Sensors - Descarga este documento en PDF. Documentación en PDF para descargar gratis. Disponible también para leer online.

School of Electronic Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin 300072, China





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Abstract A 12-bit high-speed column-parallel two-step single-slope SS analog-to-digital converter ADC for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter DAC used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC’s linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration TDI CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines-s, shows that the proposed ADC is suitable for high-speed CMOS image sensors. View Full-Text

Keywords: CMOS image sensor; column-parallel ADC; single-slope ADC; two-step CMOS image sensor; column-parallel ADC; single-slope ADC; two-step





Autor: Tao Lyu, Suying Yao, Kaiming Nie and Jiangtao Xu *

Fuente: http://mdpi.com/



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