Turbo product code decoder without interleaving resource: From parallelism exploration to high efficiency architectureReportar como inadecuado




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1 ELEC - Département Electronique 2 IMS - Laboratoire de l-intégration, du matériau au système 3 Lab-STICC TB CACS IAS Lab-STICC - Laboratoire des sciences et techniques de l-information, de la communication et de la connaissance UMR 3192

Abstract : This article proposes to explore parallelism in Turbo-Product Code TPC decoding through a parallelism level classification and characterization. From this design space exploration, an innovative TPC decoder architecture without any interleaving resource is presented. This architecture includes a fully-parallel SISO decoder capable of processing n symbols in one clock period. Syntheses results show the better efficiency of such an architecture compared with existing solutions. Considering a six-iteration turbo decoder of a BCH32,262 product code, synthesized in 90 nm CMOS technology, 10 Gb-s can be achieved with an area of 600 Kgates. Moreover, a second architecture enhancing parallelism rate is described. The throughput is 50 Gb-s while an area estimation gives 2.2 Mgates. Finally, comparisons with existing TPC decoders and existing LDPC decoders are performed. They validate the potential of proposed TPC decoder for Gb-s optical fiber transmission systems.





Autor: Camille Leroux - Christophe Jego - Patrick Adde - Deepak Gupta - Michel Jezequel -

Fuente: https://hal.archives-ouvertes.fr/



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