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1 LESTER - Laboratoire d-Electronique des Systèmes TEmps Réel 2 Lab-STICC UBS CACS MOCS Lab-STICC - Laboratoire des sciences et techniques de l-information, de la communication et de la connaissance

Abstract : In this paper, we focus on the design of a communication system based on reusing IP cores. We consider that traditional methods for hardware design at the RT level suffer from heavy limitations that prevent them from efficiently addressing the algorithmic complexity and the high flexibility required by the various application profiles. We propose to raise the abstraction level of the specification and introduce the notion of architectural flexibility of an IP core by benefiting from the emerging high-level synthesis tools. Our method has been successfully applied to the design of a Reed-Solomon RS decoder IP core, targeting the DVB-DSNG digital video broadcasting standard. We are able to generate a variety of RS decoder architectures, with varying hardware complexity and computation speed, from a single behavioral-level VHDL specification.

Autor: Bertrand Le Gal - Emmanuel Casseau - Chirstophe Jégo - Nathalie Le Héno - Eric Martin -



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