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1 Lab-STICC UBS CACS MOCS Lab-STICC - Laboratoire des sciences et techniques de l-information, de la communication et de la connaissance 2 LESTER - Laboratoire d-Electronique des Systèmes TEmps Réel

Abstract : In this paper we present a networked lightweight and par- tially reconfigurable platform assisted by a remote bitstreams server. We propose a software and hardware architecture as well as a new data-link level network protocol implementation dedicated to dynamic and par- tial reconfiguration of FPGAs. It requires a network controller and much less external memories to store reconfiguration software, bitstreams and buffer pools used by standard communication protocols. Our measures, based on a real implementation, show that our system can download re- mote bistreams with a reconfiguration speed ten times faster than known solutions.

Keywords : partial reconfiguration FPGA link layer bitstream server





Autor: Pierre Bomel - Guy Gogniat - Jean-Philippe Diguet -

Fuente: https://hal.archives-ouvertes.fr/



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