New High-Speed and Low-Power radix-2r multiplication algorithms.Reportar como inadecuado

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1 CTDA - Centre de Développement des Technologies Avancées 2 FEMTO-ST - Franche-Comté Électronique Mécanique, Thermique et Optique - Sciences et Technologies

Abstract : In this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general space-time partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products N-r, but also eliminates the need of pre-computing odd multiples of the multiplicand in higher radix r≥3 multiplication. Based on a mathematical proof that any higher radix-2r can be recursively derived from a combination of two or a number of lower radices, a series of generalized radix-2r multipliers are generated by means of primary radices: 21, 22, 25, and 28. A variety of higher-radix 23-232 two-s complement 64x64 bit serial-parallel multipliers are implemented on Virtex-6 FPGA and characterized in terms of multiply-time, energy consumption per multiply-operation, and area occupation for r value varying from 2 to 64. Compared to a recent published algorithm, savings of 21%, 53%, 105% are respectively obtained in terms of speed, power, and area.

Autor: Abdelkrim K. Oudjida - Ahmed Liacha - Mohamed L. Berrandjia - Nicolas Chaillet -



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