Design and Simulation of Nano Wire FETReportar como inadecuado

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1 Department of Electronics and communication Engineering

Abstract : As the era of classical planar metal-oxide-semiconductor field-effect transistors MOSFETs comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FETs, starting at the 22 nm technology node. Since physical limits such as short channel effect SCE and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry and 1D nanowire NW channel with gate-all-around GAA geometry to reduce SCE. High carrier mobility of single wall carbon nanotube SWNT or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. To simulate these devices, accurate modelling and design based on gate-material are necessary to assess their performance limits, since cross-sections of the multi-gate NWFETs are expected to be a few nano-meters wide in their ultimate scaling. In this paper we have explored the use of SILVACO with different materials for simulating and

Keywords : SILVACO nanowire FET threshold voltage

Autor: M Anil Kumar - Y N S Sai Kiran - U Jagadeesh - M Durga Prakash -



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