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VLSI DesignVolume 2012 2012, Article ID 242989, 10 pages

Research ArticleDepartment of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, SK, Canada S7N 5A9

Received 2 December 2011; Accepted 6 March 2012

Academic Editor: Maurizio Martina

Copyright © 2012 Muhammad Martuza and Khan A. Wahid. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The paper presents a unified hybrid architecture to compute the integer inverse discrete cosine transform IDCT of multiple modern video codecs—AVS, H.264-AVC, VC-1, and HEVC under development. Based on the symmetric structure of the matrices and the similarity in matrix operation, we develop a generalized -decompose and share- algorithm to compute the IDCT. The algorithm is later applied to four video standards. The hardware-share approach ensures the maximum circuit reuse during the computation. The architecture is designed with only adders and shifters to reduce the hardware cost significantly. The design is implemented on FPGA and later synthesized in CMOS 0.18 um technology. The results meet the requirements of advanced video coding applications.

Autor: Muhammad Martuza and Khan A. Wahid

Fuente: https://www.hindawi.com/


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