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VLSI Design - Volume 7 1998, Issue 2, Pages 163-176

Institute of Computer Design and Fault Tolerance Prof. Dr.-Ing. D. Schmid, University of Karlsruhe, Germany

Received 1 August 1996

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Fault sets that accurately describe physical failures are required for efficient patterngeneration and fault coverage evaluation. The fault model presented in this paperuniquely describes all structural changes in the transistor net list that can be caused byspot defects, including bridging faults that connect more than two nets, break faults thatbreak a net into more than two parts, and compound faults. The developed analysismethod extracts the comprehensive set of realistic faults from the layout of CMOS ICsand for each fault computes the probability of occurrence. The results obtained by thetool REFLEX show that bridging faults connecting more than two nets account for asignificant portion of all faults and cannot be neglected.

Author: Gerald Spiegel and Albrecht P. Stroele



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