Harmless, a Hardware Architecture Description Language Dedicated to Real-Time Embedded System SimulationReportar como inadecuado




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* Corresponding author 1 bau - Beirut Arab University 2 Systèmes Temps Réel IRCCyN - Institut de Recherche en Communications et en Cybernétique de Nantes 3 ESEO-TRAME - ESEO-TRAME ESEO-Tech 4 IRCCyN - Institut de Recherche en Communications et en Cybernétique de Nantes

Abstract : Validation and Verification of embedded systems through simulation can be conducted at many levels, from the simulation of a high-level application model to the simulation of the actual binary code using an accurate model of the processor. However, for real-time applications, the simulated execution time must be as close as possible to the execution time on the actual platform and in this case the latter gives the closest results. The main drawback of the simulation of application-s software using an accurate model of the processor resides in the development of a handwritten simulator which is a difficult and tedious task. This paper presents Harmless, a hardware Architecture Description Language ADL that mainly targets real-time embedded systems. Harmless is dedicated to the generation of simulator of the hardware platform to develop and test real-time embedded applications. Compared to existing ADLs, Harmless1 offers a more flexible description of the Instruction Set Architecture ISA 2 allows to describe the microarchitecture independently of the ISA to ease its reuse and 3 compares favorably to simulators generated by the existing ADLs toolsets.

Keywords : Cycle-accurate simulation Instruction set simulation Hardware architecture description language





Autor: Rola Kassem - Mikaël Briday - Jean-Luc Béchennec - Guillaume Savaton - Yvon Trinquet -

Fuente: https://hal.archives-ouvertes.fr/



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