Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test SolutionReportar como inadecuado

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1 SysMIC - Conception et Test de Systèmes MICroélectroniques LIRMM - Laboratoire d-Informatique de Robotique et de Microélectronique de Montpellier 2 INFINEON - SOPHIA - Infineon Technologies France 3 INFINEON TECHNOLOGIES FRANCE - Centre de recherche et développement international en design pour la micro-électronique

Abstract : In this paper we present an exhaustive analysis of resistive-open defect in core-cell of SRAM memories. These defects that appear more frequently in VDSM technologies induce a modification of the timing within the memory delay faults. Among the faults induce by such resistive-open defects there are static and dynamic Read Destructive Fault RDF, Deceptive Read Destructive Fault DRDF, Incorrect Read Fault IRF and Transition Fault TF. Each of them requires specific test conditions and different kind of March tests are needed to cover all these faults TF, RDF, DRDF and IRF. In this paper, we show that a unique March test solution can ensure the complete coverage of all the faults induced by the resistive-open defects in the SRAM core-cells. This solution simplifies considerably the problem of delay fault testing in this part of SRAM memories.

Autor: Luigi Dilillo - Patrick Girard - Serge Pravossoudovitch - Arnaud Virazel - Simone Borri - Magali Hage-Hassan -



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