Modeling of Poly-Silicon Carrier Transport with Explicit Treatment of Grains and Grain BoundariesReportar como inadecuado




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VLSI Design - Volume 8 1998, Issue 1-4, Pages 533-537



404 Phillips Hall, Cornell University, Ithaca, NY 14853, USA

CIS-X 333, Stanford University, Stanford, CA 94305-4075, USA



Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Explicit treatment of grains and grain boundaries is necessary to model the carriertransport in poly-silicon devices whose feature size is comparable to the grain size. Thegrain boundaries were modeled by interface traps, and comparison was made betweenthermionic and diffusion transport across the grain boundaries. It was found that thenumerical model for diffusion transport with total trap conservation in grain boundaryareas is not physically convergent and shows a strong grid sensitivity. Effects of thecritical doping level and the lattice temperature are demonstrated on poly-siliconresistors with 1-D bamboo-type and 2-D realistic microstructures.





Autor: Edwin C. Kan and Robert W. Dutton

Fuente: https://www.hindawi.com/



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