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Journal of Applied Mathematics - Volume 2015 2015, Article ID 851837, 9 pages -

Research Article

School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China

Guangxi Key Laboratory of Automatic Detecting Technology and Instrument, Guilin University of Electronic Technology, Guilin 541004, China

Received 14 October 2014; Revised 22 February 2015; Accepted 23 February 2015

Academic Editor: Hossein Torkaman

Copyright © 2015 Hongzhi Hu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper deals with the modeling of fault for analog circuits. A two-dimensional 2D fault model is first proposed based on collaborative analysis of supply current and output voltage. This model is a family of circle loci on the complex plane, and it simplifies greatly the algorithms for test point selection and potential fault simulations, which are primary difficulties in fault diagnosis of analog circuits. Furthermore, in order to reduce the difficulty of fault location, an improved fault model in three-dimensional 3D complex space is proposed, which achieves a far better fault detection ratio FDR against measurement error and parametric tolerance. To address the problem of fault masking in both 2D and 3D fault models, this paper proposes an effective design for testability DFT method. By adding redundant bypassing-components in the circuit under test CUT, this method achieves excellent fault isolation ratio FIR in ambiguity group isolation. The efficacy of the proposed model and testing method is validated through experimental results provided in this paper.





Autor: Hongzhi Hu, Shulin Tian, and Qing Guo

Fuente: https://www.hindawi.com/



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