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1 SOCRATE - Software and Cognitive radio for telecommunications Inria Grenoble - Rhône-Alpes, UCBL - Université Claude Bernard Lyon 1, CITI - CITI Centre of Innovation in Telecommunications and Integration of services 2 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE

Abstract : —High-level synthesis HLS, which enables the synthesis of custom hardware from C-C++ specification, is a big step forward in terms of design productivity, especially for FPGAs. In HLS, data-types and operators are restricted to those available in the C language supported by the compiler. This hinders the use of application-specific arithmetic, which has been proven to improve performance and resource usage in FPGA designs. In this work, we propose to study how HLS tools can use application specific knowledge to take advantage of application-specific arithmetics. Our approach is implemented within a source-to-source compiler that optimizes C source code to use non-standard, application-specific operators. Our study focuses on widely used summation-reduction patterns, which we optimize by hoisting out floating-point management out the reduction-accumulation loop. As a consequence, the original floating-point addition is replaced by a much simpler fixed-point adder, while enforcing a user specified accuracy constraint for the result. Our results demonstrates significant improvements in terms speed, resource usage and accuracy, which rival with that of RTL level implementations.

Autor: Yohann Uguen - Florent De Dinechin - Steven Derrien -



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