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VLSI Design - Volume 12 2001, Issue 3, Pages 431-448

Department of Computer Engineering and Informatics, University of Patras, Patras 26 500, Greece

Received 3 February 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Recent trends in IC technology have given rise to a new requirement, that of low powerdissipation during testing, that Built-In Self-Test BIST structures must target alongwith the traditional requirements. To this end, by exploiting the inherent properties ofCarry Save, Carry Propagate and modified Booth multipliers, in this paper we proposenew power-efficient BIST structures for them. The proposed BIST schemes are derivedby: a properly assigning the Test Pattern Generator TPG outputs to the multiplierinputs, b modifying the TPG circuits and c reducing the test set length. Our resultsindicate that the total power dissipated during testing can be reduced from 29.3% to54.9%, while the average power per test vector applied can be reduced from 5.8% to36.5% and the peak power dissipation can be reduced from 15.5% to 50.2% dependingon the implementation of the basic cells and the size of the multiplier. The testapplication time is also significantly reduced, while the introduced BIST schemesimplementation area is small.





Autor: D. Bakalist, X. Kavousianos, H. T. Vergos, D. Nikolos, and G. Ph. Alexiou

Fuente: https://www.hindawi.com/



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