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1 ICT - Institute of Computing Technology Beijing 2 Institut Montefiore - Département d-Electricité, Electronique & Informatique 3 LISTIC - Laboratoire d-Informatique, Systèmes, Traitement de l-Information et de la Connaissance

Abstract : As network link rates are being pushed beyond 40Gbps, IP lookup in high-speed routers is moving to hardware. The TCAM Ternary Content Addressable Memory-based IP lookup engine and the SRAM Static Random Access Memory-based IP lookup pipeline are the two most common way to achieve high throughput. However, route updates in both engines degrade lookup performance and may lead to packet drops. Moreover, with the growing importance of virtual IP routers where more frequent updates happen, finding solutions that both achieve fast lookup and low update overhead becomes urgent. In this paper, we propose a hybrid IP lookup architecture with fast updates. The architecture is based on an efficient trie partitioning scheme that divides the Forwarding Information Base FIB into two prefix sets: a large disjoint leaf prefix set and a small overlapping prefix set. Then, the large disjoint set is mapped into an external TCAM-based lookup engine and the small overlapping set is mapped into an on-chip SRAM-based lookup pipeline. Critical optimizations are developed on both IP lookup engines to reduce the update overhead. We show how to extend the proposed hybrid architecture to support virtual routers. Our implementation shows a throughput of 250 million lookups per second MLPS. The update overhead is significantly lower than that of previous work and the utilization ratio of most external TCAMs is up to 100\%.

Autor: Layong Luo - Gaogang Xie - Yingke Xie - Laurent Mathy - Kavé Salamatian -

Fuente: https://hal.archives-ouvertes.fr/


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