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VLSI Design - Volume 7 1998, Issue 4, Pages 353-364

xilinx Inc., 2100 Logic Drive, San Jose 95124, CA, USA

Electrical and Computer Engineering, Purdue University, West Lafayette 47907-1285, IN, USA

Received 22 February 1994; Accepted 10 July 1995

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In FPGAs the routing resources are fixed and their usage is constrained by the locationof antifuses. In addition, the antifuses affect the layout performance significantly,depending on the technology. Hence, simplistic placement level assumptions turn out tobe grossly inadequate in predicting the timing and wirability behavior of a layout.There is a need, therefore, for a layout technique which changes the layout at placementlevel based on accurate post-layout timing analysis and net wirability. In this paper weconsider such a wirability and performance driven layout flow for row-based FPGAs.Timing information from a post-layout timing analyzer and wirability informationfrom global and channel routers are used by an incremental placer to effectively perturbthe placement. A large improvement up to 29% in timing, has been obtainedcompared to non-iterative FPGA layout for a set of industrial designs and benchmarkexamples.

Autor: Sudip Nag and Kaushik Roy



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