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VLSI Design - Volume 12 2001, Issue 1, Pages 25-52


ECE and CIS Depts., NJIT, USA

Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, New Jersey 07102, USA

Received 14 June 1999; Revised 5 January 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Existing message-passing parallel computers employ routers designed for a specificinterconnection network and deal with fixed data channel width. There are disadvantagesto this approach, because the system design and development times aresignificant and these routers do not permit run time network reconfiguration. Changesin the topology of the network may be required for better performance or faulttolerance.In this paper, we introduce a class of high-performance universal staticallyand dynamically adaptable programmable routers UPRs for message-passing parallelcomputers. The universality of these routers is based on their capability to adapt at runand-or static times according to the characteristics of the systems and-or applications.More specifically, the number of bidirectional data channels, the channel size and theI-O port mappings for the implementation of a particular topology can changedynamically and statically. Our research focuses on system-level specification issues ofthe UPRs, their VLSI design and their simulation to estimate their performance. Oursimulation of data transfers via UPR routers employs VHDL code in the MentorGraphics environment. The results show that the performance of the routers dependsmostly on their current configuration. Details of the simulation and synthesis arepresented.

Autor: Taras I. Golota and Sotirios G. Ziavras

Fuente: https://www.hindawi.com/


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