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* Corresponding author 1 COMPSYS - Compilation and embedded computing systems Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l-Informatique du Parallélisme

Abstract : This report presents the Data-aware Process Networks, a new parallel execution model adapted to the hardware constraints of high-level synthesis, where the data transferts are made explicit. We show that the DPN model is consistant in the meaning where any translation of a sequential program produces an equivalent DPN without deadlocks. Finally, we show how to compile a sequential program to a DPN and how to optimize the input-output and the parallelism.

Keywords : automatic parallelization High-level Synthesis polyhedral compilation I-O optimization





Author: Christophe Alias - Alexandru Plesco -

Source: https://hal.archives-ouvertes.fr/



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