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VLSI Design - Volume 7 1998, Issue 1, Pages 1-13

Viewlogic Systems Inc., Fremont, CA 94538-6530, USA

Computer Science Department, 2130 Faner Hall, Southern Illinois University at Carbondale, Carbondale, IL 62901, USA

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In recent years there has been an extensive interest in clustering the modules of anetwork so that the maximum delay from any primary input to any primary output isminimized 8, 7, 6. Clusters have a maximum capacity and modules may have differentimplementations. All existing CAD frameworks initially select an implementation ofeach module, and at a later stage they cluster the modules. We present an approach thatclusters the nodes, while considering their alternative implementations, so that wefurther minimize the maximum delay after the clustering. Our approach is based onoptimal algorithms for restricted versions of this complex problem in circuit design, andoutperforms the conventional approach, which first obtains an implementation for eachcircuit module without considering clustering and then, in a later step, performsclustering.

Autor: Dimitrios Karayiannis and Spyros Tragoudas



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