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1 IETR - Institut d-Electronique et de Télécommunications de Rennes

Abstract : This paper details the design and implementation performances of an efficient generator of chaotic discrete integer valued sequences. The generator exhibits orbits having very large lengths compared to those given in the literature. It is implemented in C language and parallelized using the Parameterized and Interfaced Synchronous Dataflow Model of Computation PiSDF MoC. The proposed structure is shown to be scalable, parallel and time efficient. The resulting implementation combines a very long minimal chaotic sequence omin > 7*2^128 32-bit samples and a very high throughput of 173Mbps on 4 cores of a General Purpose Processor.

Keywords : multicore implementation performance analysis dataflow model of computation pseudo-random number generator Chaotic generator





Autor: Karol Desnos - Safwan El Assad - Aurore Arlicot - Maxime Pelcat - Daniel Menard -

Fuente: https://hal.archives-ouvertes.fr/



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